1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device for storing and retaining information, the non-volatile semiconductor memory device incorporating a capacitor which includes a ferroelectric film interposed between opposite electrodes, such that different polarization states of the ferroelectric film are utilized to enable the storage and retention of information.
2. Description of the Related Art
In general, a semiconductor memory device incorporating a ferroelectric material (hereinafter referred to as a "ferroelectric semiconductor memory device") is a non-volatile semiconductor memory device which stores and retains data based on the polarization directions of the ferroelectric film. Hereinafter, examples of conventional non-volatile ferroelectric semiconductor memory devices will be described (see, for example, Japanese Laid-open Patent Publication No. 6-223583, U.S. Pat. No. 4,873,664, and the like).
FIG. 4 is a circuit diagram illustrating a conventional non-volatile semiconductor memory device. FIG. 8 is a circuit diagram illustrating a sense amplifier 30 employed in the semiconductor memory device shown in FIG. 4. FIG. 5 is a timing diagram illustrating the timing scheme of the semiconductor memory device shown in FIG. 4. FIG. 6 is a graph showing the hysteresis characteristics of a ferroelectric film used in a capacitor in a main memory cell (hereinafter referred to as a "main memory cell capacitor") of the conventional semiconductor memory device. FIG. 7 is a graph showing the hysteresis characteristics of a ferroelectric film used in a capacitor in a dummy memory cell (hereinafter referred to as a "dummy memory cell capacitor") of the conventional semiconductor memory device.
With reference to the circuit diagram of FIG. 4 illustrating the conventional non-volatile semiconductor memory device, a bit line (BIT) 26 and a bit line (/BIT) 28 are coupled to a sense amplifier 30. Main memory cells 20a, 20b, and 20c and a dummy memory cell 46 are coupled to the bit line (BIT) 26, whereas main memory cells 20d and 20e and a dummy memory cell 36 are coupled to the bit line(/BIT) 28.
The main memory cell 20a includes a MOS transistor 24 and a main memory cell capacitor 22. The main memory cell capacitor 22 includes a ferroelectric film interposed between first and second electrodes. A gate of the MOS transistor 24 is coupled to a word line 32; a drain of the MOS transistor 24 is coupled to the bit line (BIT) 26; and a source of the MOS transistor 24 is coupled to the first electrode of the main memory cell capacitor 22. The second electrode of the main memory cell capacitor 22 is coupled to a cell plate line 34.
Similarly, the dummy memory cell 36 includes a MOS transistor 38 and a dummy memory cell capacitor 40. The dummy memory cell capacitor 40 includes a ferroelectric film interposed between first and second electrodes. A gate of the MOS transistor 38 of the dummy memory cell 36 is coupled to a dummy word line 42; a drain of the MOS transistor 38 is coupled to the bit line (/BIT) 28; and a source of the MOS transistor 38 is coupled to the first electrode of the dummy memory cell capacitor 40. The second electrode of the dummy memory cell capacitor 40 is coupled to a dummy cell plate line 44.
As shown in FIG. 8, the sense amplifier 30 includes p-MOS transistors 110, 111, and 112; and n-MOS transistors 118 and 120. Reference numerals 114 and 116 respectively correspond to the bit line (BIT) 26 and the bit line (/BIT) 28.
Hereinafter, the operation of the above conventional non-volatile semiconductor memory device will be described with reference to the timing diagram shown in FIG. 5, the graph of FIG. 6 showing the hysteresis characteristics of the ferroelectric film in a main memory cell capacitor, and the graph of FIG. 7 showing the hysteresis characteristics of the ferroelectric film in a dummy memory cell capacitor.
In each of the hysteresis characteristics graphs of FIGS. 6 and 7, the horizontal axis represents an electric field which is applied to the memory cell capacitor, with the corresponding charge being represented on the vertical axis. As seen from FIGS. 6 and 7, a capacitor incorporating a ferroelectric film functions in such a manner that a remanent polarization exists (as indicated at points B, E, H, and K) even when the applied field is zero. In a non-volatile semiconductor memory device, such remanent polarization is utilized for retaining data in a non-volatile manner. The main memory cell capacitor takes a state at point B (FIG. 6) when data "1" is stored in the memory cell, and takes a state at point E (FIG. 6) when data "0" is stored in the memory cell. The dummy memory cell capacitor takes an initial state at point K (FIG. 7). For the sake of explanation, it is assumed that the bit line (BIT) 26 and the bit line (/BIT) 28, the word line 32, the dummy word line 42, the cell plate line 34 and the dummy cell plate line 44 are at a logic voltage "L" (=ground potential "GND") during an initial state which exists before a reading of the data in the main memory cell occurs; thereafter, the bit line (BIT) 26 and the bit line (/BIT) 28 are placed in a floating state; and an inverted sense signal (/SE) is at a logic voltage "H" (=supply voltage "Vcc").
Next, as shown in FIG. 5, the word line 32, the dummy word line 42, the cell plate line 34 and the dummy cell plate line 44 all shift to their respective logic voltages "H". It is assumed that the logic voltage "H" for the word line 32 is a high voltage (Vpp) obtained by elevating the supply voltage (Vcc), whereas the logic voltages "H" for dummy word line 42, the cell plate line 34, and the dummy cell plate line 44 are the supply voltage (Vcc). Thus, the MOS transistor 24 of the main memory cell 20a and the MOS transistor 38 of the dummy memory cell 36 are turned on so that an electric field is applied across the main memory cell capacitor 22 and the dummy memory cell capacitor 40. If data "1" is stored in the main memory cell, the state of the main memory cell shifts from point B to point D (FIG. 6) so that the difference Q1 between the charges at point B and point D is read out, which appears as a voltage on the bit line (BIT) 26. The state of the dummy memory cell shifts from point K to point J (FIG. 7) so that the difference Qd between the charges at point K and point J is read out, which appears as a voltage on the bit line (/BIT) 28. Then, the inverted sense signal (/SE) shifts to its logic voltage "L" (i.e., the ground voltage), so that the difference between the voltage from the main memory cell which has been read onto the bit line (BIT) 26 and the voltage from the dummy memory cell which has been read onto the bit line (/BIT) 28 is amplified by the sense amplifier 30, and the bit line (BIT) 26 is brought up to the supply voltage level (Vcc) and the bit line (/BIT) 28 is brought down to the ground voltage level (GND). Thus, the data "1" in the main memory cell is read.
On the other hand, if data "0" is stored in the main memory cell, the state of the main memory cell shifts from point E to point D (FIG. 6) so that the difference Q0 between the charges at point E and point D is read out, which appears as a voltage on the bit line (BIT) 26. The state of the dummy memory cell shifts from point K to point J (FIG. 7) so that the difference Qd between the charges at point K and point J is read out, which appears as a voltage on the bit line (/BIT) 28. Then, the difference between the voltage from the main memory cell which has been read onto the bit line (BIT) 26 and the voltage from the dummy memory cell which has been read onto the bit line (/BIT) 28 is amplified by the sense amplifier 30, and the bit line (BIT) 26 is lowered to the ground voltage level (GND) and the bit line (/BIT) 28 is brought up to the supply voltage level (Vcc) . Thus, the data "0" in the main memory cell is read.
As a result of the amplification by the sense amplifier 30, the bit line (BIT) 26 is placed at the supply voltage level (Vcc) when data "1" is stored in the main memory cell, the cell plate line 34 also being at the supply voltage level (Vcc). As a result, no electric field is applied across the main memory cell capacitor 22 (point E in FIG. 6). Thereafter, in order to restore the data stored in the main memory cell capacitor 22 to point B, the cell plate line 34 is placed at the ground voltage (point A in FIG. 6), and then the word line 32 is placed at its logic voltage "L". As a result, no electric field is applied across the main memory cell capacitor 22 (back to point B in FIG. 6). Thus, the data "1" has been rewritten to the main memory cell. Usually, in the state corresponding to point A, the elevated voltage (Vpp) is supplied to the word line 32 so that the logic voltage "H" on the bit line (BIT) 26 is sufficiently supplied to the main memory cell capacitor 22.
Similarly, when data "0" is stored in the main memory cell, the bit line (BIT) 26 is at the ground voltage, whereas the cell plate line 34 is at the supply voltage level (Vcc). Therefore, the main memory cell capacitor 22 is at point D in FIG. 6. Thereafter, the cell plate line 34 is placed at its logic voltage "L", so that no electric field is applied across the main memory cell capacitor 22 (point E in FIG. 6). Then, the word line 32 is placed at its logic voltage "L", but no electric field is still applied across the main memory cell capacitor 22, so that the main memory cell remains at point E in FIG. 6. Thus, the data "0" has been rewritten to the main memory cell.
With respect to the dummy memory cell, when data "1" is stored in the main memory cell, the bit line (/BIT) 28 is at the ground voltage (GND) and the dummy cell plate line 44 is at the supply voltage (Vcc), so that the dummy memory cell capacitor 40 is at point J in FIG. 7. Thereafter, as the dummy word line 42 is placed at the ground voltage, the dummy cell plate line 44 is also concurrently placed at the ground voltage. As a result, no electric field is applied across the dummy memory cell capacitor 40 (back to point K in FIG. 7).
Similarly, when data "0" is stored in the main memory cell, the bit line (/BIT) 28 is at the supply voltage (Vcc) and the dummy cell plate line 44 is also at the supply voltage (Vcc), so that the dummy memory cell capacitor 40 is at point K in FIG. 7. Thereafter, as the dummy word line 42 is placed at the ground voltage, the dummy cell plate line 44 is also concurrently placed at the ground voltage, but still no electric field is applied across the dummy memory cell capacitor 40, so that the dummy memory cell remains at point K in FIG. 7. Thus, data has been rewritten to the dummy memory cell.
However, the above-described conventional non-volatile semiconductor memory device has the following problem:
Since the sense amplifier sense-amplifies the lower voltage levels of the bit lines only to the ground voltage in the conventional non-volatile semiconductor memory device, it is difficult to attain sufficient polarization in the memory cell capacitor. As a result, in the case where data "0" is stored in the main memory cell, it is impossible to provide a large voltage margin between the bit lines during a sense operation.